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Channel: Why is acquire semantics only for reads, not writes? How can an LL/SC acquire CAS take a lock without the store reordering with the critical section? - Stack Overflow
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Answer by Netch for Why is acquire semantics only for reads, not writes? How can an LL/SC acquire CAS take a lock without the store reordering with the critical section?

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I have got an answer from other source that I would consider finally proper; here is my translation and rewording.

The principle that disallows instruction misordering is not some kind of implicit memory barrier - it could have been not implemented at all, and the operation will still be correct - but the fact that spinlock acquiring is checked and, unless it succeeds, a thread shall not continue with data access. The AArch64 example code (from the same answerer) is:

; Spinlock Acquire
    PRFM PSTL1KEEP, [X1] ; preload into cache in unique state
Loop
    LDAXR W5, [X1] ; read lock with acquire
    CBNZ W5, Loop ; check if 0
    STXR W5, W0, [X1] ; attempt to store new value
    CBNZ W5, Loop ; test if store succeeded and retry if not
; loads and stores in the critical region can now be performed
    STR X25, [X10]
; Spinlock Release
    STLR WZR, [X1] ; clear the lock with release semantics

STXR itself could have been reordered with other following accesses but, due to next CBNZ, it will not allow committing of following instructions unless STXR succeeds. (CPU may, in general, do some execution of them if predicts it would be useful, but shall not commit their results unless execution unambiguously reaches them.)

This looks obvious when explained but wasn't yet so before, seems my bad :(

(The answerer suggested reading section K11 of ARM® Architecture Reference Manual (ARMv8) for more details.)

However this doesn't refute, in any way, need for representing LL/SC pair atomically to other participants, if this is required - that is an nearly orthogonal question.


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